Senior Staff Design Engineer, Mixed Signal and High Speed IO
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 15 years of experience in analog mixed signal or high-speed IO development.
- Experience defining and taking to High Volume Manufacturing (HVM) leading edge mixed-signal or high-speed IO designs.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on wireline silicon architecture and design.
- Experience with technical innovation in mixed-signal and high-speed IO solutions.
- Experience working on high-performance, data-center class IP, from concept through high-volume deployment.
About the job
Our portfolio spans CPU, TPU, Networking and other key data center technologies, which power Google's most demanding Compute and AI/ML applications.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
- Architect and design high-speed analog/digital circuits (ADC, DAC, PLL, CDR, DSP), including optimizing for Power, Performance, and Area (PPA).
- Model and simulate channel behavior (S-parameters), signal integrity, and jitter using tools like MATLAB.
- Bring up new silicon, characterize performance, and test for electrical compliance in lab environments.
- Work with packaging, board design, and firmware teams to ensure seamless integration into System-on-Chips (SoCs).
- Adhere to standards like IEEE or OIF for high-speed protocols and optimize power consumption.
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