ASIC Design Verification Engineer, Devices and Services
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 3 years of experience verifying digital logic at RTL level using SystemVerilog or C/C++.
- Experience creating and using verification components and environments in standard verification methodology.
- Experience verifying digital systems using standard IP components/interconnects (i.e., microprocessor cores, hierarchical memory subsystems).
- Experience with scripting languages and software development frameworks.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Science or equivalent practical experience.
- Experience in one or more of the following areas: Caches Hierarchies, Coherency, Memory Consistency Models, DDR/LPDDR, PCIe, Packet Processors, Security, Clock and Power Controllers.
- Experience with Interconnect Protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL).
- Experience with performance verification of SOCs, pre-Silicon analysis and post-Silicon correlation.
- Experience with building verification methodologies that span simulation, emulation and FPGA prototypes.
About the job
Responsibilities
- Plan and execute the verification of the next generation configurable Infrastructure IPs, interconnects and memory subsystems.
- Create and enhance constrained-random verification environments using SystemVerilog and UVM.
- Develop cross language tools and verification methodologies.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct blocks and subsystems and close coverage measures to identify verification holes and to show progress towards tape-out.
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