Silicon RTL Design Engineer, Google Cloud
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science or a related field, or equivalent practical experience.
- 4 years of experience in ASIC development with Verilog/SystemVerilog, Very High Speed Integrated Circuit (VHSIC), Hardware Description Language (VHDL), or Chisel.
- Experience with micro-architecture and designing IPs and subsystems.
- Experience in one coding/scripting language (e.g., Python, Perl).
Preferred qualifications:
- Experience in System on a Chip (SoC) designs and integration flows.
- Experience in AI/ML.
- Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
- Knowledge of high performance and low power design techniques.
About the job
In this role, you will be part of a team developing Application-Specific Integrated Circuit (ASICs) used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design to specify and deliver quality designs for next generation data center accelerators. You will solve technical problems with micro-architecture and practical reasoning solutions, and evaluate design options with complexity, performance, power.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
- Drive design methodology, libraries, debug, code review in coordination with other IP Design Verification (DV) teams and Physical Design teams.
- Identify and drive power, performance and area of improvements.
- Participate in design, implementation and integration of chassis and subsystems.
- Perform RTL coding for Subsystems/SoC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks.
- Perform quality check flows like Lint, CDC, RDC, VCLP.
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