Senior CPU RTL Design Engineer, Subsystem
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience in high-performance CPU or AI accelerator logic/RTL design/integration including microarchitecture definition and PPA optimizations.
- Experience with a HDL language and front-end design methodology.
- Experience with CPU, cache subsystem integration with SOC.
- Experience with RTL static checks, like lint and CDC.
Preferred qualifications:
- Experience with ARM Instruction Set Architecture.
- Experience with SOC design, architect, and integration.
- Experience with real-time operating systems (e.g. Android).
- Experience with DFT, sensor integration, debug architecture.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Participate in developing CPU or AI accelerator design and deliveries into SOC.
- Develop CPU subsystem front-end designs, emphasizing on microarchitecture and RTL design for the next generation CPU.
- Deliver designs that meet PPA and functional goals with modern techniques, interpret the techniques into design constructs, and languages in order to participate in SOC integration effort.
- Work with the verification team to ensure production of quality designs, and the physical design and power teams to meet frequency, power, and area goals.
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