ASIC Design For Testability Engineer, Silicon
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Minimum qualifications:
- Bachelor's or Master's degree or equivalent practical experience.
- 5 years of experience with Design for Testability/Design for Debugging (DFT/DFD) flows and methodologies.
- Experience in developing DFT specifications and DFT architecture.
- Experience in fault modeling, test standards and industry DFT/DFD/Automatic Test Pattern Generation (ATPG) tools with Application-Specific Integrated Circuit (ASIC) DFT, synthesis, simulation and verification flow.
Preferred qualifications:
- Experience with DFT for a subsystem with multiple physical partitions.
- Experience with Internal JTAG (IJTAG) ICL, Procedural Description Language (PDL) terminology, ICL extraction, Instrument Connectivity Language (ICL) modeling with Siemens Tessent Tool.
- Experience with Spyglass-DFT, DFT Scan constraints and evaluating DFT Static Timing Analysis (STA) paths.
- Experience with coding language like Perl or Python.
- Knowledge of DFT techniques like SSN, HighBandwidth IJTAG.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities
- Work with Design for testing (DFT) engineers, Register-Transfer Level (RTL), Physical Designer Engineers, System on a chip (SoC) DFT and Product Engineering team.
- Work on Subsystem level DFT scan, Memory Built-In Self Test (MBIST) Architecture with multiple voltage, power domains.
- Write scripts to automate the DFT flow.
- Develop tests that can be used for Production in the Automatic Test Equipment (ATE) flow.
- Work with members of the DFT team to deliver two or more Subsystems in a SoC.
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