Design Verification Manager
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience in Design Verification.
- 4 years of experience in people management, developing employees.
- Experience constructing reusable verification components and environments using Universal Verification Methodology (UVM), System Verilog or similar.
- Experience in Portable Stimulus Standard (PSS), formal or emulation based SimXL methodologies.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering or Computer Science, or a related field.
- Experience in one or more of the following like Operating Systems, Memory Management, Caches Hierarchies, Coherency, Memory Consistency Models, Memory Ordering, Double Data Rate (DDR)/Low Power Double Data Rate (LPDDR), Peripheral Component Interconnect Express (PCIe), or Packet Processors.
- Experience working with software teams to define hardware/software interfacing including control/status registers, security, and error handling.
- Experience with Formal verification techniques, System Verilog Assertions (SVA) and assertion-based verification.
- Experience building verification methodologies that span simulation, emulation and Field Programmable Gate Array (FPGA) prototypes.
About the job
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Lead and manage verification activities for complex Slow-Slow (SS) or System on a Chip (SoC).
- Develop all aspects of logic verification infrastructure and methodology for complex mobile SoC Internet Protocol (IP) or SS blocks.
- Collaborate with design teams to ensure integration of verification methodology into the design process.
- Optimize and improve verification methodologies to increase efficiency and effectiveness.
- Collaborate with both external and internal Computer Aided Design (CAD) teams to develop new verification solutions that can improve the quality and efficiency.
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