Senior Design Verification Engineer, Silicon
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience with Design Verification of Subsystem (SS) or SoC designs.
- Experience in Python or Perl for automating verification environments, data processing including digital logic, pipeline architectures and common bus protocols (e.g., AXI, AHB).
- Experience in SystemVerilog (SV) and UVM for ASIC/IP verification.
- Experience in building Portable Stimuli based test/test bench framework.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience in domains such as Low-Power verification, Unified Power Format, Performance Analysis, or Security Verification.
- Experience with hardware acceleration platforms such as ZeBu, Palladium, or Veloce for SoC validation and knowledge of high-speed interconnects (e.g., PCIe, CHI, ACE) and memory subsystems.
- Experience in ML/AI based Verification flows and methodologies along with knowledge of post-silicon bring-up and using pre-silicon environments to reproduce and root-cause silicon sightings.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities
- Architect and implement constrained-random stress scenarios to identify corner-case failures in designs.
- Develop and integrate C-based embedded tests with SystemVerilog/Universal Verification Methodology (UVM) environments to validate driver-to-hardware interactions.
- Build and maintain reusable UVM-based verification components (agents, predictors, and scoreboards) and infrastructure.
- Drive verification closure across multiple platforms, ensuring seamless test bench portability from RTL simulation to emulation/acceleration goals.
- Design and enhance scripting-based utilities for regression management, automated bug triaging, and coverage analysis.
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