Head of Packaging Development Engineering, Silicon
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, related degree or equivalent practical experience.
- 15 years of experience in packaging development.
- 8 years of experience in people management.
- Experience in packaging and substrate technology, including but not limited to Flip Chip Chip Scale Package (FCCSP), Package on Package (POP), FOPLP, SxS and Chiplet packaging.
- Experience in the packaging design and SIPI workflows and optimizing them for continuously improved results.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, related degree or equivalent practical experience.
- Knowledge of SoC physical design.
- Knowledge of the overall system design.
- Knowledge of system level interactions between mobile device components, including application processors, memory, PMIC, and others.
- Ability to navigate organizational dynamics and lead multiple teams and suppliers across several time zones.
About the job
As a Packaging Development Manager, you will lead our mobile silicon packaging efforts. You will plan our packaging technology development, package design, and Signal and Power Integrity (SIPI) teams. In addition, you will work with silicon Intellectual Property (IP) design teams, implementation teams, system design teams, Power Management Integrated Circuit (PMIC) teams, and power teams to architect and optimize the product Power Delivery Network (PDNs). You will also work with the internal/external high speed interface IP teams, implementation teams, and system teams to ensure all the high speed IPs (PCIe, USB, UFS, CSI, DSI, LPDDR, etc.) meet the performance goals. You will also generate and provide the hardware design guidance and support to the system teams and Automated Test Equipment (ATE) hardware teams.
In this role, you will provide leadership to other silicon engineers in a changing environment to build relationships with our packaging supplier and internal operations partners. You will drive technical projects from the concept/planning stage through execution to volume production.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
The US base salary range for this full-time position is $227,000-$320,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Plan our packaging technology development efforts to survey the engaged landscape, develop, qualify and deliver packaging technologies. Working with foundry or Outsourced Semiconductor Assembly and Test (OSAT) suppliers.
- Lead our packaging design efforts to enable exceptional mobile silicon power and performance.
- Manage our Signal Integrity and Power Integrity efforts to ensure the wider product level Power Delivery Network (PDN) is optimized, all the high speed interfaces (e.g., PCIe, USB, UFS, CSI, DSI, LPDDR, etc.) meet the performance goals, generate and provide the hardware design guidance and support to the system teams and Automated Test Equipment (ATE) hardware teams.
- Work with our commercial and product engineering teams on packaging and component vendor management.
- Work with the Pixel team to meet system level thermal, electrical and mechanical requirements.
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